The present invention relates to a novel composition of an apparatus for die bonding which is performed as a step in the process of assembling a semiconductor chip in a package.
In assembling a semiconductor chip in a package, the chip has to be fixed on a die pad at a predetermined location in the package prior to wire bonding and this step is called die bonding.
Die bonding methods are classified into three general types, the eutectic alloy method, the soldering method, and the resin bonding method. In the Au-Si eutectic alloy method, an Au-plated die pad is heated at about 400.degree. C. in a N.sub.2 or N.sub.2 +H.sub.2 atmosphere with the back surface of the Si chip being pressed against the surface of the Au layer so as to form a Au-Si eutectic alloy layer that establishes a bond between the chip and the die pad. In the soldering method, the back surface of a semiconductor chip is metallized with a thin film of Ni-Au or Ti-Ni-Au, and the chip and the substrate metal with a small piece of Pb-Sn solder held therebetween are heated at 200.degree.-300.degree. C. in a N.sub.2 or a N.sub.2 +H.sub.2 atmosphere, thereby bonding the chip to the die pad. The resin bonding method is a fairly new technique and employed having the particles of an electroconductive material (e.g. Ag) dispersed therein. The adhesive resin is coated on the die pad by either stamping or with a dispenser and the chip temporarily fixed on the die pad by pressing is heated so as to cure the resin. In each of these methods of die bonding, the chip is properly positioned and fixed on the die pad by being sucked with a collet (grip means) while, the chip is connected to the package electrically or thermally.
In the die bonding methods described above, the chip sucked with the collet is thermally compressed to a preform (e.g. Au/Si layer, brazing filler material or epoxy resin) on the die pad, but this often causes the preform to go beyond the interface between the chip and the die pad and either solidify in ball form around the chip or climb the lateral side of the chip soiling the device in either case.